The present invention relates to a process of manufacturing semiconductor devices and, in particular, to a process of transferring such patterns as rotation error check patterns, resolution check patterns and alignment check patterns used in a lithography process therefor.
The lithography process which is one of the steps of the semiconductor device manufacturing process requires that the pattern is formed to be precisely aligned with an underlying pattern and also that the pattern is formed in a predetermined size. In a step-and-repeat reduction projection system which is widely used in the lithography step or process, there occur, if the system is not properly adjusted, such problems as rotation errors in image formation patterns which are caused by rotation or movement of a reticle and as image surface curving or image surface slanting in which the image formation surface is not in parallel with the semiconductor wafer faces. Any of such problems make it impossible to achieve the desired patterns. It is necessary to discover such problems as they occur and to make sufficient and suitable adjustment.
With respect to the conventional step-and-repeat reduction projection system, such errors have been controlled through routine examination using a test reticle thereby confirming that no errors are beyond the desired precision limits in all ranges of projection.
However, by relying only on routine examination or inspection, there is a possibility that some disastrous abnormality or defects are built in during the manufacturing process by oversight of a step-and-repeat reduction projection system having problems and that the defective semiconductor devices thus made are processed to the next step leading to large manufacturing losses.
In addition, even if such problems do exist in the manufacturing step of the product as described above, they are often overlooked in other tests in other steps because such other tests having different judgment standards directed to an external appearance do not uncover such problems in the product, resulting in the defective product being discovered only in the last measurement test for the wafer step. Thus, such problems can lead to large losses.